To satisfy emerging domains’ burgeoning demand for compute power and energy efficiency, computer architects have turned to specialized hardware accelerators and novel physical devices. Integrating these components not only requires significant engineering efforts, but also introduces overheads due to their diverse characteristics and mismatches with the conventional software/hardware stack. Reconfigurable architectures are a promising solution to ease system integration as well as to balance versatility and performance. In particular, field-programmable gate arrays (FPGA) can interact with novel hardware at bit and cycle level, while coarse-grained reconfigurable arrays (CGRA) can organize heterogeneous components into efficient, spatial pipelines.
This talk will first give an overview of Princeton Reconfigurable Gate Array (PRGA), an open-source framework for building customized, physical-design-friendly FPGAs with co-generated RTL-to-bitstream toolchains. PRGA lays the foundation for my future work on integrating novel hardware components into domain-specialized FPGAs. Then, I will present Duet, a cache-coherent, manycore-FPGA system that facilitates fine-grained workload partitioning between processors and reconfigurable accelerators. PRGA and Duet are both validated on multiple silicon prototypes which I led/co-led. I will present these prototypes and share the insights I gained through the experience from architecture design to chip evaluation.
Ang Li is a Ph.D. candidate in the department of Electrical and Computer Engineering at Princeton University, advised by Prof. David Wentzlaff. He received B.Sc. in Electronic Engineering from Tsinghua University in 2016 and M.A. in Electrical Engineering from Princeton University in 2018. He is interested in all aspects of computer architecture and VLSI design, especially heterogeneous and reconfigurable architectures. He is an experienced chip builder and an active contributor to multiple open-source projects.