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Emerging Memory Technology Challenges

Gurtej Sandhu


As the cell dimensions continue to shrink below 20 nm for NAND Flash, the fundamental scaling challenges include charge per cell and cell to cell interference. NAND bit cost has been driving the market demand in the recent past. It is becoming increasingly difficult to maintain the cell scaling trend and maintain a low cost structure. 3D NAND may mitigate some of the cost and technology limitations but appear to provide a limited potential for sustained scaling. Memory technologies based on alternative storage mechanisms are required in order to surmount the constraints imposed by physics of charge based storage devices. For example, some of the candidates for alternate memory technologies may include phase change, conductive bridge, resistance change, spin torque transfer etc. However, there are several performance requirements which limit selection of any one of these technologies as a universal solution for the memory market. Some of these challenges will be identified and potential solutions discussed.


Gurtej S. Sandhu is Director of Advanced Technology developments at Micron Technology, Inc. In his current role, he manages the Emerging Memory Technologies research and development at Micron. He received his Masters in electrical engineering at the Indian Institute of Technology, New Delhi and a Ph.D. degree in physics at the University of North Carolina, Chapel Hill, in 1990. Dr. Sandhu then joined Micron Technology, where he has been in a number of engineering and management roles responsible for process technology development, pilot manufacturing and transfers to manufacturing. He has been actively involved with a broad range of process technologies, such as ion implantation, deposition technologies, plasma processing, CMP, Litho and front-end and back-end module integration technologies for IC processing. He has been associated with microelectronics technology for over 20 years and has pioneered a number of process technologies which are currently employed in mainstream semiconductor chip manufacturing. Moreover, he was involved with introduction of a number of Atomic Layer Deposition (ALD) based processes and innovative patterning techniques for memory chip technology. Dr. Sandhu has authored over 35 technical papers and has several hundred issued U.S. patents. Dr. Sandhu is Fellow of IEEE.

Gurtej Sandhu Headshot
Gurtej Sandhu
EEB 105
22 Feb 2011, 10:30am until 11:30am