Abstract
Integrated circuit feature size scaling inherently causes the technology to become more susceptible to electrostatic discharge induced damage. This fact has led to many recent, creative efforts in design of ESD protection devices. Although protection devices function well from a reliability point of view, they load the I/O pads at which they are placed. This is problematic for I/Os that must transmit or receive signals in the GHz range–the shunt admittance associated with the protection device reduces the gain, increases the noise figure, and affects the impedance matching. The result is that ESD protection circuit design and active circuit design can no longer be done in isolation from each other. In this talk, I will discuss how concurrent design of RF and ESD protection circuitry can be done so as to provide both excellent performance and reliability.
Biography
Elyse Rosenbaum received the B.S. degree (with distinction) from Cornell University in 1984, the M.S. degree from Stanford University in 1985, and the Ph.D. degree from the University of California, Berkeley in 1992. Her study program was electrical engineering. From 1984 through 1987, she was a Member of Technical Staff at AT&T Bell Laboratories in Holmdel, New Jersey. She is currently an Associate Professor in the Department of Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign.
Dr. Rosenbaum’s present research interests include design, modeling and simulation of ESD protection circuits, gate oxide reliability, analysis of substrate noise coupling, and silicon-on-insulator. She has presented tutorials on reliability physics at the International Reliability Physics Symposium and the EOS/ESD Symposium. She has authored or co-authored 70 technical papers and is an editor for IEEE Transactions on Device and Materials Reliability. Dr. Rosenbaum has been the recipient of a Best Student Paper Award from the IEDM, a Technical Excellence Award from the SRC, and an NSF CAREER award.
