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High-Bandwidth Microprocessor Packaging

Henning Braunisch

Abstract

Continued scaling of microprocessor performance is based on many-core architectures and leads to a rapid scaling of processor input/output (I/O) bandwidth, making microelectronic packaging at the component and system levels a prime concern when considering metrics such as I/O power efficiency. We discuss standard microelectronic packaging based on organic materials and its extensions, propagation loss due to surface roughness, and high-speed chip-to-chip interconnect prototypes operating at up to 20 gigabits per second.

Biography

Henning Braunisch received M.S. degrees in electrical engineering from Michigan State University, East Lansing, in 1995, and the University of Hanover, Germany, in 1996, and the Ph.D. degree in electrical engineering and computer science from the Massachusetts Institute of Technology (MIT), Cambridge, in 2001. He has since been with Intel Corporation, Components Research, Chandler, Arizona, where he holds the job title of Principal Engineer. His research interests and expertise are in advanced microelectronic packaging and applied electromagnetics. Dr. Braunisch is a Senior Member of the IEEE, a Member of the Institute of Physics, London, UK, and an Affiliate Associate Professor at the University of Washington, Seattle. Dr. Braunisch holds 33 US patents and has co-authored more than 80 technical papers that were published in peer-reviewed journals or presented at international conferences. He was the lead author of the ECTC 2006 Best Poster Paper and the ECTC 2007 Best Paper and was a recipient of the SRC GRC Mahboob Khan Outstanding Mentor Award in 2008 and 2013. Dr. Braunisch is a Past Chair of the IEEE Phoenix Section and Program Chair for ECTC 2015.

Henning Braunisch Headshot
Henning Braunisch
Intel Corp.
EEB 105
2 Dec 2014, 10:30am until 11:30am