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Lowering Costs & Barriers to Chip Design

Mehdi Saligane


Given the critical role of the semiconductor industry in national security, economic growth, and overall well-being, it is crucial to address the challenges faced by traditional chip design ecosystems. High design costs, limited access to fabrication, hard-to-use tools, and inadequate design support are among the obstacles that hinder the overall IC design productivity. Due to its custom nature, manual design has been the norm for most analog blocks, while digital flow has been extensively automated. This lack of custom circuit automation leads to long design cycles and costs. As such, adopting innovative and agile practices such as automation, reusability, reproducibility, and open collaboration is essential to expedite chip-building efforts and pave the way to improve productivity in the semiconductor industry.

This talk will give an overview of Michigan’s Fully Autonomous System-on-Chip (FASoC) synthesis tool, a collaborative project developed as part of the DARPA IDEA program and based on proprietary EDA tools. It aims to address the need for custom circuit design generation and tackles this problem by using a cell-based design generation methodology to build various analog and mixed-signal (AMS) blocks. Several SoCs have been produced using this framework, including ones in 180nm, 130-nm, 65-nm, 16nm and 12-nm. As part of the current open-source effort, I will also go through the OpenFASOC project developed on top of OpenROAD, GDSfactory, and other open tools for push-button circuit to layout generation. This work strives to bridge the gaps between EDA software and hardware by leveraging our expertise to develop new tools that optimize the hardware design process. This talk offers insights into novel methodologies that can advance the semiconductor industry by leveraging modern software practices into hardware. I will also cover our efforts on various automated circuit generators and implemented designs targeting hardware security, rapid prototyping, and enabling niche communities.


Mehdi Saligane is a Research Scientist and Intermittent Lecturer in the Electrical Engineering and Computer Science department at the University of Michigan, Ann Arbor. He received his B.S. in Electrical Engineering and Computer Science from Ecole Polytechnique in Grenoble, France, in 2009, his M.S. in Electrical Engineering and Computer Science from the University of Grenoble, France, in 2011, and his Ph.D. degree in Electrical Engineering from the University of Aix-Marseille in 2016. His current research interests are in low-power and energy-efficient IC design, with a recent focus on open-source EDA and analog and mixed-signal IC design automation.

He is the recipient of the Google Cloud Research Innovators award and the Google Research Faculty Award in 2023 and 2021, respectively.  Dr. Saligane currently serves as chair of the Analog Working Group, as a member of the Technical Steering Committee at CHIPS Alliance, and as a technical member of SSCS’ open source ecosystem. He is also the co-founder and organizer of the SSCS Code-a-Chip Notebook Competition at ISSCC and the SSCS Chipathon Design Contest.

Mehdi Saligane Headshot
Mehdi Saligane
University of Michigan, Ann Arbor
ECE 403
14 Mar 2023, 10:30am until 11:30am