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Power management of high performance microprocessors

Tanay Karnik


The presentation will provide an introduction to Intel Labs University Collaborative Research. This will be followed by a review of advanced power management techniques that have been employed in leading designs. Aggressive technology scaling has enabled very high transistor integration capacity. Complex functions are integrated into hardware with multiple heterogeneous cores and caches. Managing total power consumption has emerged as the most challenging task in today’s highly complex microprocessor systems. Independent per-core dynamic voltage scaling is proven to be an effective way to minimize power consumption. It needs multiple voltage rails supplied by independent voltage regulators. Traditionally, the regulators are based on the system platform and utilize large discrete passive components. Due to the size and routing planes, the number of independent platform rails is limited to a very small number. Integrated voltage regulators provide a practical solution. They operate at a high switching frequency, employ small passive components and hence provide large number of ultra-fast independent voltages. This presentation includes a survey of recent research in integrated voltage regulators at Intel.


Tanay Karnik is Director of Intel Labs University Research Office. He received his Ph.D. in Computer Engineering from the University of Illinois at Urbana-Champaign and joined Intel Corporation in 1995. His research interests are in the areas of variation tolerance, power delivery, soft errors and physical design. He has published over 45 technical papers, has 51 issued and 30 pending patents in these areas. He received an Intel Achievement Award for the pioneering work on integrated power delivery. He has presented several keynotes, invited talks and tutorials, and has served on 5 PhD students’ committees. He was a member of ISSCC, DAC, ICCAD, ICICDT and ISQED program committees and JSSC, TCAD, TVLSI, TCAS review committees. Tanay was the General Chair of ASQED’10, ISQED’08, ISQED’09 and ICICDT’08. Tanay is an IEEE Senior Member, an ISQED Fellow, an Associate Editor for TVLSI and a Guest Editor for JSSC.

Tanay Karnik Headshot
Tanay Karnik
EEB 105
20 Nov 2012, 10:30am until 11:30am