The rapid proliferation of wireless communication devices and standards has been driven in large part by Moore’s law, according to which the availability of digital processing capability for a given power constraint doubles roughly every 18 months. Modern wireless communication devices leverage this capability by using sophisticated signaling and coding schemes; examples of this include MIMO-OFDM systems and newer coding techniques that allow the system to operate closer to the Shannon limit at the expense of complex demodulation and decoding requirements. Additionally, channel bandwidths have also been increasing leading to higher data rates and network throughput. Underpinning the technology advance is the requirement for manufacturing robustness. The cost of future system-on-chip solutions must be limited by the billions of digital gates rather than the relatively few mixed-signal and radio frequency functional blocks. Hence, RF transceivers that are digitally calibrated against process, voltage, and temperature variations are becoming necessary.
In this talk, the use of digital calibration in RF transceivers is illustrated by way of several examples. In the competitive global system for mobile communications (GSM) market, for example, transceiver integrated circuits should exhibit low power, small form factor, multi-band capabilities, low cost, etc. These goals are met in a quad-band GSM transmitter design. Previous GSM transmitters use Bipolar, BiCMOS, SiGe and CMOS technologies and architectures that have evolved from mixer-based to phase-locked-loop (PLL)-based topologies. Although the PLL-based approach promises superior performance, previous analog implementations are sensitive to process, voltage, and temperature (PVT) variations, substrate noise coupling, etc. A PLL-based transmitter using closed-loop PLL up-conversion via a modulated fractional-N frequency synthesizer with digital auto-calibration is exploited in this work. A primary objective is to implement a mostly digital transmitter in a low cost CMOS technology. Attenuation of high frequency modulation data by the low pass response of the analog PLL loop is compensated by the high pass response of a digital compensation filter. Because an exact inverse relationship is required between the analog PLL and digital compensation filter transfer functions that is robust against PVT variations, a digital calibration technique is used to align the inverse functions.
In another example, a low-IF WCDMA receiver that offers a level of integration comparable to that of the popular direct-conversion architecture while avoiding its dc offset, 1/f noise, and second-order non-linearity problems is described. The low-IF technique has not previously been implemented in a WCDMA receiver because the required image rejection ratio (IRR) is problematic over the WCDMA band (3.84MHz) at low IF frequencies. With the low-IF chosen as half the channel spacing (2.5MHz), the required image rejection ratio is equal to the WCDMA specified adjacent channel rejection ratio (>40dB).
An image rejection scheme employing a passive phasing technique consumes less current and introduces fewer noise sources than the active double quadrature mixer method. The phasing method applied to a down-converter requires a wideband 90 degree phase difference network that exhibits an inherent phase error that depends on the network complexity and the bandwidth ratio in the image rejection band. Parasitics of the large passive components required for implementation of the low frequency 90 degree phase shift network also cause phase errors. Both effects have impeded the development of low-IF WCDMA receivers.
The dual-conversion low-IF receiver avoids the direct-conversion drawbacks and exceeds the IRR specifications. A dual conversion image-rejection block down-converts the received signal to a low-IF of 2.5MHz and rejects image signals. The viability of a low-IF receiver meeting stringent IRR specifications is demonstrated for the first time via an IR down converter for WCDMA applications in a single poly, six metal, 1.8V, 130nm CMOS process. It uses a Gilbert mixer for the first down-conversion, a digitally corrected quadrature LO generator (DCQLO) and a masking quadrature mixer (MQM) for accurate quadrature LO mixing, and a five-stage passive polyphase filter (PPF) for the 90 degree phase-shift function.
Other examples will be presented as time permits.
David J. Allstot received the B.S., M.S., and Ph.D. degrees from the Univ. of Portland, Oregon State Univ., and the Univ. of California, Berkeley, respectively. He has held several industrial and academic positions and has been the Boeing-Egtvedt Chair Professor of Engineering at the University of Washington since 1999. Dr. Allstot is the recipient of several outstanding teaching, research, and service awards He has advised approximately 75 M.S. and Ph.D. graduates and published about 175 papers. He is a Member of Eta Kappa Nu and Sigma Xi and a Fellow of the IEEE.