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Transistor Scaling: Past, Present, Future

Dr. Mark Stettler


The continual demand for more powerful computing has resulted in more functionality, greater circuit density, and smaller transistors on successive generations of microprocessors. Amazingly, these scaled transistors, engineered on a nanometer scale, not only continue to operate robustly as switches as they are made smaller but also have better performance. This talk examines the principles and the technology used to improve transistor performance in the past, present, and for the future.


Mark Stettler was born in Huntsville, Alabama in 1966. He received a B.S. in Electrical Engineering from the University of Notre Dame in 1988 and a Ph.D. in Electrical Engineering from Purdue University in 1993 with a thesis entitled “Scattering Matrix Studies of Silicon Devices.” He joined Intel’s TCAD department in 1994 supporting 0.25 micron process development. Mark now manages the Process and Device Modeling group, which supports device and process modeling and applications, compact model development, and process file extraction for Intel’s Technology Manufacturing Group. He has contributed to 40 publications on semiconductor simulation and process development.

Dr. Mark Stettler Headshot
Dr. Mark Stettler
EEB 105
2 Nov 2010, 10:30am until 11:30am