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UW ECE Launches New BSECE Degree Program

14/16nm ASIC Design

Taylor and team recently designed the Tiered Accelerator Fabric architecture, and with collaborators taped out a 511-core RISC-V implementation in TSMC 16 nm, including 5 Linux-capable RISC-V cores, 496-core RISC-V manycore, and a binarized neural network.


Research Areas