By Wayne Gillam | UW ECE News
Over the last few years, the world has seen great advances in computing power as evidenced by popular artificial intelligence and machine learning applications such as Uber, Siri, and most recently, ChatGPT. At the same time, these types of applications and the large numbers of devices that use them have been placing ever-greater demands on data centers that support cloud computing, which serves as a backbone for information technology. As one might expect, the need for computational speed, power and capacity has been growing exponentially.
Overall, growth in computing power is continuing to keep pace with these demands, following Moore’s law, which states that the speed and capability of computers can be expected to double every two years as a result of increases in the numbers of transistors that a microchip can contain. However, what is not keeping pace with this rapid evolution are the networking components between computing and memory devices in data centers. This presents a serious problem, because even if robust computing power is available, it will always be limited by the speed and bandwidth of whatever network it is plugged into.
UW ECE Assistant Professor Sajjad Moazeni, who was recently featured in UW News, has been tackling this problem through research supported by a 2022 NSF CAREER award. His work is focused on developing a new type of computer chip and network architectures for use in data centers that support AI and machine learning applications. This effort is aimed at increasing data center network speed, capacity, and energy efficiency. Now, his work will be augmented by a 2023 Google Research Scholar Program award, which will allow Moazeni to further expand this research.
“I’ve been working on proposing some ideas for the physical implementation of this chip while conducting system-level simulations and modeling,” Moazeni said. “I’m very grateful to Google, because this award and support helps me and my team to expand the scope of the system-level modeling that we are doing.”
The Google Research Scholar Program provides unrestricted gifts to support research at institutions around the globe, and it is focused on funding world-class research conducted by early-career professors. 2023 award recipients were announced online this summer and include Moazeni and UW ECE alumnus Vikram Iyer (Ph.D. ‘21), who is an assistant professor in the Paul G. Allen School of Computer Science & Engineering.
Smart, co-packaged optics in a chip
Moazeni is developing a “smart” silicon photonic chip, which can serve as a bridge between electrical and optical signals for a computer processor. And because it is a smart chip, it can also assist the processor with computing tasks, such as memory access and data retrieval across a large network of devices. In electrical and computer engineering, this smart chip is known as a type of “co-packaged optics,” so named because of its role as an electro-optical interconnect and its proximity to the computer processor.
“Typically, people look at a silicon photonic chip as a kind of co-packaged technology that acts as an electro-optical bridge. It takes the electrical data and converts it into optical signals, and it usually just talks directly to the processor,” Moazeni said. “Here, what we wanted to do was to add some compute power on top of this into the chip, and then have it communicate with the memory as well. So, the chip is going to be more than just an electro-optical converter. It’s going to do some processing on top of that. That’s why we call it a smart chip.”
This smart chip is very energy efficient and could dramatically increase computing capacity of networked devices. Moazeni estimates that the chip will be approximately 10 times more energy efficient than current interconnect approaches, and it will be able to achieve 10 to 100 times higher bandwidth. He also noted that the smart chip could spur further improvements in data center device networks.
“If this smart chip enables the energy efficiency and the high bandwidth with the data densities we are targeting, then it could enable new system-level architectures,” Moazeni said. “Today, data center architecture is based on the limitations of networking. So, if we can improve network connectivity, it can enable new architectures.”
Technology with broad impact
The technology Moazeni is developing promises to have a broad impact on society and the world at large. In addition to helping data centers better handle the demands of popular AI and machine learning applications, this smart chip and new network architectures Moazeni is proposing and developing will enable advances in any area reliant on computing speed, power, and capacity. This, for example, could include things such as AI-driven drug discovery and medical diagnosis, predicting global weather patterns, forecasting climate change, working out complex supply-chain logistics and supporting air traffic control — a wide range of applications relevant and vital to modern life.
Moazeni plans to continue this research over at least the next four years, and he emphasized the importance of improving network speed, capacity, and energy efficiency.
“We’ve probably increased computational power more than 100 times over the last decade, but we are reaching the end of Moore’s law, and even now, you cannot gain that much from a computing power increase anymore,” Moazeni said. “So, as we move forward, we definitely need to focus on closing the gap between computing and network communication. That’s what this smart chip and redesign of existing network architectures will help us to do.”
For more information about this research, which is supported by an NSF CAREER award and a Google Research Scholar Program award, contact Sajjad Moazeni. More information about Moazeni’s work in a broader context can be found in this recent UW News article.